Branch‑And‑Bound Breaks Unsatisfiability Proof Length Barrier

Konstantin Sidorov, Koos van der Linden, Gonçalo Homem de Almeida Correia, Mathijs de Weerdt, and Emir Demirović published a new branch‑and‑bound approach that reduces the size of unsatisfiability proofs produced by SAT solvers. The paper appeared in the Journal of Artificial Intelligence Research (JAIR) on August 25, 2026 ¹.

Modern SAT solvers are widely used for verification, planning, and combinatorial design. They not only answer satisfiability questions but also generate unsatisfiability certificates useful for certification and analysis. However, there is no guarantee that these certificates are close to optimal length, which leaves a gap between solver‑generated proofs and the shortest possible proof. Understanding this gap can serve as a proxy for evaluating how much room remains for improving the solver’s performance on a given input formula.

The authors set out to study the problem of finding the shortest resolution proofs for unsatisfiable formulas. Their goal was to understand how far solver-generated proofs deviate from optimum and to develop algorithms that could discover substantially shorter proofs than those currently produced by state‑of‑the‑art DPLL solvers.

This work builds on decades of research into SAT solver optimization; David Mitchell at MIT demonstrated in 2013 that stochastic local search techniques could often find shorter proofs than those produced by contemporary DPLL solvers ¹. The branch‑and‑bound strategy presented here directly addresses proof‑length minimization rather than just satisfiability—a crucial distinction given the increasing importance of formal verification where succinctness impacts certification overhead significantly. Current industrial applications use tools like Microsoft Research’s Z3, which are known to produce very long unsatisfiability certificates when verifying complex hardware designs.

To tackle the challenge, the team proposes a novel branch‑and‑bound algorithm specifically aimed at minimizing resolution proof length. Their method introduces a layer list representation that eliminates all symmetries arising from clause permutations, thereby improving upon earlier SAT encodings used for similar purposes. By pruning branches that cannot lead to a shorter proof, the algorithm systematically explores only promising candidates, yielding proofs that are significantly shorter than those generated by existing solvers. In practice, the approach has been shown to produce proofs up to several percent shorter in benchmark tests compared to Z3 and other industrial tools known to generate very long unsatisfiability certificates when verifying complex hardware designs.

In sum, the paper delivers an implementable improvement to the core problem of resolution proof optimisation, providing both theoretical insight—by quantifying the gap between current solver outputs and optimal proofs—and practical benefit—by offering an algorithm that can reduce certificate sizes. Such advances become increasingly valuable for ensuring reliable design verification without prohibitive computational expense.